This invention derives from the schematic structure of the previously disclosed photovoltaic emitter according to WO 2010/089624 in the name of the same inventors Zbigniew T. KUZNICKI and Patrick MEYRUEIS, which is incorporated herein by way of reference.
This previous photovoltaic device is able to exploit high energy photons, in particular UV and visible photons, in addition to near IR photons, said device comprising a slab, wafer or chip of p-type or n-type photovoltaic material produced according to the method claims of WO 2010/089624, having a top surface intended to be exposed to photonic radiation, having a built-in P-N junction delimiting an emitter part and a base part, having front and rear carrier collection and extraction means and comprising at least one area or region specifically designed or adapted to absorb high energy or energetic photons and located adjacent or near at least one hetero-interface. This device is characterised in that said slab, wafer or chip of photovoltaic material comprises also at least one metamaterial field or region forming a low-energy secondary carrier generation cavity, which is contiguous or proximate to the at least one absorption area or region for the energetic photons and subjected to a built-in or applied electrical field having an intensity sufficient to withdraw and move away the secondary electrons libe-rated by the primary hot electrons from their initial sites within the concerned metamaterial area or region, at a speed sufficient to prevent their return into said metamaterial region or field, thus forming a substructure performing multistage conversion, wherein the density of divacancies within the metametallic field(s) or region(s) is greater than 1018 divacancies/cm3, preferably greater than 1019 diva-cancies/cm3, most preferably greater than 1020 divacancies/cm3 and the conduction between the metamaterial and the respectively adjacent n-type material has a time constant which is at the most of the same magnitude that the secondary carrier generation time constant, wherein the thickness of the or each planar amorphous semiconductor material layer is comprised between 10 nm and 50 nm and wherein the width of the respectively associated metamaterial field(s) or re-gion(s), in the shape of (a) continuous or discontinuous layer(s), is less than 10 nm, the semiconductor material having preferably a thickness comprised with-in 5 μm and 500 μm, preferably between 10 μm and 280 μm.
This previous invention is also characterised by a carrier collection limit designated here as CCL which is the limit separating the emitter in two parts: the upper emitter which is an electronically dead zone, and the lower emitter which is electronically fully active. As shown on FIG. 1, the converter is composed of a surface layer connected to a front grid electrode and a base connected to a rear electrode and between them an emitter structure divided in an upper emitter and a lower emitter. The thicknesses of the upper and lower emitters are respectively designated as <<du>> and <<dl>> (FIG. 1). These upper and lower emitters are separated by the limit zone called CCL for the Carrier Collection Limit. This photovoltaic emitter structure is readily visible on FIG. 1 on which the CCL limit is shown by a solid black line.
The CCL can be defined as the interface with its potential barrier blocking generated carriers to move towards the PN collection junction. So the carriers of opposite signs generated within the upper emitter cannot be collected because it is not possible for them to be separated one each from the other with regard to the CCL.
The goal of this present invention is multiple.
The first one is to proceed with the collection of the whole photo-generated population of free carriers from all components of the light-to-electricity converter i.e. particularly from the upper emitter located between the front face and the nanoscale silicon layered system.
The second one is to reduce and preferably to cancel the CCL effect in order to considerably increase the conversion efficiency.
The last one is to improve further the conversion efficiency by suitable modifications of the amorphized silicon layer.
This enhancement is obtained through this present invention by means of at least a double transformation which results of an amorphization beam that scans the silicon wafer. The suitable scanning process leads to discontinous or locally thinned and very thin amorphized layer. The process can be performed by an ion beam implantation process or an electron beam irradiation process. The ions can be for example, silicon or phosphorous ions.
The CCL effect is suppressed by a suitable structure discontinuity or by, for example, the tunnel conduction across locally thinned CCL.
In such a case, the structure conveys carriers through limited special thin zones the carriers that have to reach the collection PN junction. They can pass through the crystalline passages of the buried substructure or through the very thin zones where the thickness of the buried structure is so reduced that the tunnel conduction effect can appear. All these passages have to be not too much spaced with respect of the carrier movements along the buried substructure, i.e. movements perpendicular to the collecting PN junction.
These and other benefits of this invention will become clear from the following description by reference to the drawings.